The present invention relates to integrated circuit devices and, more particularly, to ferroelectric devices, such as memory devices, and methods for manufacturing the same.
Ferroelectric memory devices using ferroelectric layers have been considered as an alternative approach for certain memory applications, such as smart cards and the like. Such devices may have non-volatile characteristics that sustain previous data without supplied power and may operate with low power consumption in a manner similar to that of dynamic random access memory (DRAM) and static random access memory (SRAM).
Ferroelectric memory devices are generally divided into two categories. The first category includes devices using a ferroelectric capacitor as described, for example, in U.S. Pat. No. 5,523,964. The second category includes devices having a ferroelectric field emission transistor (FET) as described, for example, in U.S. Pat. No. 5,198,994. These devices may provide higher-speed read and write operations and/or lower power consumption than other types of memory devices.
FIG. 1 is a cross-sectional view illustrating a conventional ferroelectric memory device. As shown in FIG. 1, a field isolation layer 12 is disposed in an integrated circuit (semiconductor) substrate 10 to define active region(s) 14. A plurality of gate electrodes 20 (i.e., word lines) are disposed crossing over the active regions 14. Source and drain regions 18 and 16 are formed in the active region 14 adjacent to the gate electrodes 20. A first bottom interlayer dielectric layer 24 is formed on the substrate 10 with the gate electrodes 20 thereon. Bit lines 26 connected to the drain region 18 are disposed penetrating through the first bottom interlayer dielectric layer 24. A second bottom interlayer dielectric layer 28 is formed on a surface of the first bottom interlayer dielectric layer 24 including the bit lines 26. A storage node plug 32 is connected to each of the source regions 18, penetrating the second and first bottom interlayer dielectric layers 28 and 24. A source pad 22s may be disposed on the source region 18 and a drain pad 22d may be disposed on the drain region 16. The storage node plug 32 and the bit line 26 may be connected to the source pad 22s and the drain pad 22d, respectively. Capacitors 40, which are connected to the storage node plugs 32, respectively, are formed on the second bottom interlayer dielectric layer 28. Each of the capacitors 40 includes a bottom electrode 34, a capacitor dielectric layer 36 and a top electrode 38. The bottom electrode 34 is directly in contact with the storage node plug 32, the capacitor dielectric layer 36 is placed on the bottom electrode 34 and the top electrode 38 is disposed on the capacitor dielectric layer 36.
A top insulating layer 42 is formed on the substrate including the capacitors 40. The top insulating layer 42 includes contact holes 44 exposing top surfaces of each the capacitors 40. A plate electrode 46 is formed in the contact hole 44 and directly in contact with the top surfaces of the capacitors 40. Conventionally, the capacitors 40 are disposed on the second bottom interlayer dielectric layer 28 along rows and columns defining a memory array and the plate electrodes 46 are directly in contact with the capacitors 40 arranged on one row, respectively.
Because the plate electrodes 46 of the conventional ferroelectric memory device are connected to the capacitors arranged on a row, respectively, as integration density increases, capacitor area and intervals between capacitors may decrease and the contact holes 44 exposing a top surface of the capacitor may be difficult to form. When the contact holes 44 are formed, the aspect ratio of the contact hole may be high due to the relatively thick top insulating layer 42. As a result, it may be difficult to deposit the plate electrode 46 and contact resistance may increase.